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1 ? fn3044.3 hs-82c85rh radiation hardened cmos static clock controller/generator the intersil hs-82c85rh is a high performance, radiation hardened cmos clock controller/generator designed to support systems utilizing radiat ion hardened static cmos microprocessors such as the hs-80c86rh. the hs-82c85rh contains a crystal controlled oscillator, reset pulse conditioning, halt/resta rt logic, and divide-by-256 circuitry. these features pr ovide the means to stop the system clock, stop the clock osci llator, or run the system at a low frequency (clk/256), enhanci ng control of static system power dissipation and allowing system shut-down during periods of external stress. static cmos circuit design insures low operating power and permits operation with an external frequency source from dc to 15mhz. crystal controlled operation to 15mhz is guaranteed with the use of a parallel, fundamental mode crystal and two small load capacitors. outputs are guaranteed compatible with both cmos and ttl specifications. the intersil hardened field cmos process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. specifications for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical specifications for these devices are contained in smd 5962-95820. a ?hot-link? is provided on our homepage for downloading. http://www.intersil.com/military/ features ? electrically screened to smd # 5962-95820 ? qml qualified per mil-prf-38535 requirements ? radiation hardened - total dose. . . . . . . . . . . . . . . . . . . . . 100 krad(si) (max) - transient upset . . . . . . . . . . . . . . . . . . . .>10 8 rad(si)/s - latch up free epi-cmos ? very low power consumption ? pin compatible with nmos 8285 and intersil 82c85 ? generates system clocks for microprocessors and peripherals ? complete control over system clock operation for very low system power - stop-oscillator - stop-clock - low frequency (slo) mode - full speed operation ? dc to 15mhz operation (dc to 5mhz system clock) ? generates both 50% and 33% duty cycle clocks (synchronized) ? uses either parallel mode crystal circuit or external frequency source ? hardened field, self-aligned, junction isolated cmos process ? single 5v supply ? military temperature range . . . . . . . . . . . -55c to +125c ordering information ordering number internal mkt. number part marking temp. range (c) package pkg. dwg. # 5962r9582001vjc hs1-82c85rh-q q 5962r95 82001vjc -55 to +125 24 ld sbdip d24.6 5962r9582001vxc hs9-82c85rh-q q 5962r95 82001vxc -55 to +125 24 ld flatpack k24.a 5962R9582001QJC hs1-82c85rh-8 q 5962r95 82001vjc -55 to +125 24 ld sbdip d24.6 5962r9582001qxc hs9-82c85rh-8 q 5962r95 82001vxc -55 to +125 24 ld flatpack k24.a data sheet april 20, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2000, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn3044.3 april 20, 2007 pinouts 24 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t24 top view 24 lead ceramic metal seal flatpack package (flatpack) mil-std-1835 cdfp4-f24 top view 1 2 3 4 5 6 7 8 9 10 11 12 csync pclk aen1 rdy1 ready rdy2 aen2 clk gnd clk50 start slo /fst 16 17 18 19 20 21 22 23 24 15 14 13 v dd x2 async efi f/c res s2 /stop s1 s0 x1 osc reset 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 1 slo /fst csync pclk aen1 rdy1 ready rdy2 aen2 clk gnd clk50 start v dd s0 s1 s2 /stop reset res x1 x2 async efi osc f/c pin descriptions pin pin number type description x1 x2 23 22 i o crystal connections: x1 and x2 are the crystal os cillator connections. the crystal frequency must be three times the maximum desired processor clock frequ ency. x1 is the oscillator circuit input and x2 is the output of the oscillator circuit. efi 20 i external frequency in: when f/c is high, clk is generated from the efi input signal. this input signal should be a square wave with a frequency of three times the maximum desired clk output frequency. f/c 19 i frequency/crystal select: f/c selects either the crystal oscillator or the efi input as the main frequency source. when f/c is low, the hs-82c85rh clocks are derived from the crystal oscillator circuit. when f/c is high, clk is generated from the efi input. f/c cannot be dynamically switched during normal operation. start 11 i a low-to-high transition on start will restart the clk, clk50 and pclk outputs after the appropriate restart sequence is completed. when in the crystal mode (f/c low) with the oscillator stopped, t he oscillator will be restarted when a start command is received. the clk, clk50 and pclk out puts will start after the oscillator input signal (x1) reaches the schmitt trigger input threshold and an 8k internal counter reac hes terminal count. if f/c is high (efi mode), clk, clk50 and pclk will rest art within 3 efi cycles after start is recognized. the hs-82c85rh will restart in the same mode (slo /fst) in which it stopped. a high level on start disables the stop mode. s0 s1 s2 /stop 13 14 15 i i i s2 /stop , s1, s0 are used to stop the hs-82c85rh clock outputs (clk, clk50, pclk) and are sampled by the rising edge of clk. clk, clk50 and pclk are stopped by s2 /stop , s1, s0 being in the lhh state on the low-to-high transition of clk. this lhh state must follow a passive hhh state occurring on the previous low-to-high clk transition. clk and clk50 stop in the high state. pclk stops in it?s current state (high or low). when in the crystal mode (f/c ) low and a stop command is issued, the hs-82c85rh oscillator will stop along with the clk, clk50 and pclk outputs. when in the efi mode, only the clk, clk50 and pclk outputs will be halted. the oscillator circuit if operational, will continue to run. the oscillator and/or clock is restarted by the start input signal goi ng true (high) or the reset input (res ) going low. hs-82c85rh
3 fn3044.3 april 20, 2007 slo /fst 12 i slo /fst is a level-triggered input. when high, the clk and clk50 outputs run at the maximum frequency (crystal or efi frequency divided by 3). when low, clk and clk50 frequencies are equal to the crystal or efi frequency divided by 768. slo /fst mode changes are internally synchronized to eliminate glitches on the clk and clk50. start and stop control of the oscillator or efi is available in either the slow or fast frequency modes. the slo /fst input must be held low for at least 195 osc/ef i clock cycles before it will be recognized. this eliminates unwanted frequency changes which coul d be caused by glitches or noise transients. the slo /fst input must be held high for at least 6 osc/ efi clock pulses to guarantee a transition to fast mode operation. clk 8 o processor clock: clk is the clock output used by the hs-80c86rh processor and other peripheral devices. when slo /fst is high, clk has an output frequenc y which is equal to the crystal or efi input frequency divided by three. when slo /fst is low, clk has an output frequency which is equal to the crystal or efi input frequency di vide by 768. clk has a 33% duty cycle. clk50 10 o 50% duty cycle clock: clk50 is an auxiliary cl ock with a 50% duty cycle and is synchronized to the falling edge of clk. when slo /fst is high, clk50 has an output frequency which is equal to the crystal or efi input frequency divided by 3. when slo /fst is low, clk50 has an output frequency equal to the crystal or efi input frequency divided by 768. pclk 2 o peripheral clock: pclk is a peripheral clock si gnal whose output frequency is equal to the crystal or efi input frequency divided by six and has a 50% duty cycle. pclk frequency is unaffected by the state of the slo /fst input. osc 18 o oscillator output: osc is the output of the internal oscillator circuitry. its frequency is equal to that of the crystal oscillator circuit. osc is unaffected by the state of the slo /fst input. when the hs-82c85rh is in the crystal mode (f/c low) and a stop command is issued, the osc output will stop in the high state. when the hs-82c85rh is in the efi mode (f/c high), the oscillator (if operational) will continue to run when a st op command is issued and osc remains active. res 17 i reset in: res is an active low signal which is used to generate reset. the hs-82c85rh provides a schmitt trigger input so that an rc connection can be used to establish the power-up reset of proper duration. res starts crystal oscillator operation. reset 16 o reset: reset is an active high signal which is used to reset the hs-80c86r h processor. its timing characteristics are determined by res . reset is guaranteed to be high for a minimum of 16 clk pulses after the rising edge of res . csync 1 i clock synchronization: csync is an active hi gh signal which allows multiple hs-82c85rhs to be synchronized to provide multiple in-phase clock signals. when csync is high, the internal counters are reset and force clk, clk50 and pclk into a high state. when csync is low, the internal counters are allowed to count and the clk, clk50 and pclk outputs are active. csync must be externally synchronized to efi. aen1 aen2 3 7 i i address enable: aen is an active low signal. aen serves to qualify its respective bus ready signal (rdy1 or rdy2). aen1 validates rdy1 while aen2 validates rdy2. two aen signal inputs are useful in system configurations which permit the processor to access two multi-master system buses. rdy1 rdy2 4 6 i i bus ready: (transfer complete). rdy is an active high signal which is an indication from a device located on the system data bus that data has been rece ived, or is available. rdy1 is qualified by aen1 while rdy2 is qualified by aen2 . async 21 i ready synchronization select: async is an input which defines the synchronization mode of the ready logic. when async is low, two stages of ready sy nchronization are provided. when async is left open or high a single stage of ready synchronization is provided. ready 5 o ready: ready is an active high signal which is used to inform the hs-80c86rh that it may conclude a pending data transfer. gnd 9 i ground v dd 24 i +5v power supply pin descriptions (continued) pin pin number type description hs-82c85rh
4 fn3044.3 april 20, 2007 ac test circuit notes: 1. r = 370 at v = 2.25 for clk and clk50 outputs. 2. r = 494 at v = 2.87 for all other outputs. 3. c l = 50pf. 4. c l includes probe and jig capacitance. functional diagram reset pulse conditioning logic sync logic speed select 256 or 1 clock logic ( 3) peripheral clock ( 6) restart logic external frequency select ready select oscillator stop logic ready sync res (17) start (11) (16) reset csync (1) slo /fst (12) f/c (19) x2 (22) x1 (23) s2 /stop (15) s1 (14) so (13) rdy1 (4) aen1 (3) aen2 (7) rdy2 (6) async (21) (8) clk (10) clk50 (2) pclk (18) osc (5) ready restart efi (20) selected osc osc halt sync master osc (24) v dd (9) gnd from output under test v dd c l (note 4) r (notes 1, 2) hs-82c85rh
5 fn3044.3 april 20, 2007 waveforms figure 1. waveforms for clocks note: all timing measurements are ma de at 1.5v, unless otherwise noted. figure 2. waveforms for ready si gnals (for asynchronous devices) t elel t eleh t ehel t ohch t ohcl t clch t chcl t clcl t clc50l t 5chcl t 5clch t olch t clpl t plph t phpl t clph t yhyl t ehyl t yheh t ch1ch2 t cl2cl1 1.0v 3.5v clk and clk50 efi i osc o clk o clk50 o pclk o csync i clk rdy1, 2 aen1, 2 async ready t r1vch t clr1x t a1vr1v t r1vcl t clr1x t rylcl t clayx t ryhch t cla1x t ayvcl hs-82c85rh
6 fn3044.3 april 20, 2007 figure 3. waveforms for ready si gnals (for synchronous devices) figure 4. clock stop (f/c high or f/c low) waveforms (continued) clk rdy1, 2 aen1, 2 async ready t clr1x t r1vcl t a1vr1v t r1vcl t clr1x t rylcl t clayx t ryhch t cla1x t ayvcl t rsvch efi clk clk50 pclk s0 s1 s2 /stop res start t stop t chsx t svch t svch t chsx hs-82c85rh
7 fn3044.3 april 20, 2007 figure 5. clock start (f/c high) figure 6. clock start (f/c low) figure 7. reset timing (clk running with f/c low - osc mode; clk running - or stopped with f/c high efi mode) waveforms (continued) efi clk clk50 pclk s0 s1 s2 /stop res start t start start osc clk clk50 pclk t shsl t ost crystal oscillator startup time 8192 cycles res clk reset t clil t i1hcl t clil t i1hcl t rst t shsl hs-82c85rh
8 fn3044.3 april 20, 2007 figure 8. reset timing oscillator stopped (f/c low) note: clk, clk50, pclk remain in the high state until res goes high and 8192 valid oscillator cycle s have been registered by the hs-82c85rh internal counter t ost time period). after res goes high and clk, clk50, pclk become active, the reset output will remain high for a minimum of 16 clk cycles (t rst ). figure 9. slo/fst timing overview figure 10. fast to slow clock mode transition note: if t sfpc is not met on one edge of pclk, slo /fst will be recognized on the next edge of pclk. waveforms (continued) res clk reset t rst t clil 8192 cycles osc startup time t ost osc t shsl efi or osc pclk slo /fst clk clk50 efi or osc pclk slo /fst clk clk50 t sfpc t sfpc (note) 195 efi or osc cycles (note) hs-82c85rh
9 fn3044.3 april 20, 2007 figure 11. slow to fast clock mode transition note: if t sfpc is not met on one edge of pclk, slo /fst will be recognized on the next edge of pclk. waveforms (continued) efi or osc pclk slo /fst clk clk50 t sfpc t sfpc (note) 3 efi pulses (note) figure 12. clock high and low time (using x1, x2) figure 13. clock high and low time (using efi) figure 14. ready to clock (using x1, x2) figure 15. ready to clock (using efi) ? c l = 50pf load ? load ? clk clk50 f/ c csync x1 x2 c 1 c 2 15mhz load ? load ? clk clk50 f/ c csync efi pulse generator v dd load ? load ? clk ready aen1 f/ c rdy2 aen2 csync vdd trigger pulse generator osc x1 x2 c1 c 2 15mhz load ? load ? clk ready efi f/ c aen1 rdy2 aen2 csync pulse generator v dd trigger pulse generator hs-82c85rh
10 fn3044.3 april 20, 2007 burn-in circuits static configuration notes: 5. r = 10k 10%. 6. v dd = 6.0v 5%. 7. t a = 125c min. 8. package code: sz (24 lead dip). 9. f0 is 50% duty cycle square wave pulse burst. f0 is left low after pulse burst. dynamic configuration notes: 10. r = 10k 10%. 11. v dd = 6.0v 5% (burn-in); v dd = 5.5v 5% (life test). 12. t a = 125c min. 13. package code: sz (24 lead dip). 14. f0 = 10khz, 50% duty cycle. 15. f1 = f0/2; f2 = f1/2; f3 = f2/2, f4 = f3/2; f5 = f4/2. 1 4 5 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 2 3 6 7 v dd f0 1 4 5 8 9 10 11 12 2 3 6 7 v dd load load f0 f3 f6 f5 f4 f2 f3 f1 f4 load load load f0 load load load 2.7k 2.7k v dd 16 17 18 19 20 21 22 23 24 15 14 13 irradiation circuit notes: 16. r = 47k 10%. 17. pins tied to v ss (0v): pin 9. 18. pins with loads: 2, 5, 8, 10, 16, 18, 22. 19. pins tied to v dd : 1, 3, 4, 6, 7, 11 - 15, 17, 19 - 21, 23, 24. 20. v dd = 5.5v 0.5v. load 1 4 5 8 9 10 11 12 load 2 3 load 6 7 load load 5.5v load load load 5.5v 2.7k 2.7k 16 17 18 19 20 21 22 23 24 15 14 13 hs-82c85rh
11 fn3044.3 april 20, 2007 functional description the hs-82c85rh static clock controller/generator provides simple and complete control of static cmos system operating modes. the hs-82c85rh can operate with either an external crystal or an external frequency source and can support full speed, slow, stop-clock and stop-oscillator operation. while it is directly compatible with the intersil hs-80c86rh cmos 16-bit static microprocessor, the hs-82c85rh can also be used for general purpose system clock control. separate signals are provided on the hs-82c85rh for stop and start control of the crystal oscillator and clock outputs. a single control line determines fast (crystal/efi frequency divided by 3) or slow (crystal /efi frequency divided by 768) mode operation. a clock synchronization input is provided to allow the use of multiple hs-82c85rhs in the same system. the hs-82c85rh generates the proper hs-80c86rh reset pulse, and it also handles all data transfer timing by generating the hs-80c86rh ready signal. automatic maximum mode hs -80c86rh software halt instruction decode logic is present to ease the design of software-based clock cont rol systems and provides complete software control of stop mode operation. automatic minimum mode soft ware halt instruction decoding can be easily implemented with a single 74hc74 device. restart logic insure s valid clock start-up and complete synchronization of clk, clk50 and pclk. static operating modes the hs-82c85rh static clock controller can be dynamically set to operate in any one of four modes at any one time: fast, slow, stop-clock and stop-oscillator. each mode has distinct power and performance characteristics which can be matched to the needs of a pa rticular system at a specific time (see table 1). keep in mind that a single system may require all of these operating modes at one time or another during normal operation. a design need not be limited to a single operating mode or a specific combination of modes. the appropriate operating mode can be matched to the power-performance level needed at a specific time or in a particular circumstance. reset logic the hs-82c85rh reset logic provides a schmitt trigger input (res ) and a synchronizing flip-flop to generate there set timing. the reset signal is synchronized to the falling edge of clk. a simple rc network can be used to provide power-on reset by utilizing this function of the hs-82c85rh. when in the crystal oscillator (f/c = low) or the efi (f/c = high) mode, a low state on the res input will set the reset output to the high state. it will also restart the oscillator circuit if it is in th e idle state. the reset output is guaranteed to stay in the high state for a minimum of 16 clk cycles after a low-to-high transition of the res input. an oscillator restart count s equence will not be disturbed by reset if this count is already in progress. after the restart counter expires, the reset output will stay high at least for 16 periods of clk before going low. reset can be kept high beyond this time by a continuing low input on the res input. if f/c is low (crystal oscillator mode), a low state on res starts the crystal oscillator circuit. the stopped outputs remain inactive, until the oscillator signal amplitude reaches the x1 schmitt trigger input threshold voltage and 8192 cycles of the crystal oscillato r output are counted by an internal counter. after this count is complete, the stopped outputs (clk, clk50, pclk) start cleanly with the proper phase relationships. this 8192 count requirement in sures that the clk, clk50 and pclk outputs will meet minimum clock requirements and will not be affected by unstable oscillator characteristics which may exist during the oscillator start-up sequence. this sequence is also followed when a start command is issued while the hs-82c85rh oscillator is stopped. table 1. static system operating mode characteristics operating mode description power level performance stop-oscillator all syste m clocks and main clock oscillator are stopped maximum savings slowest respons e due to oscillator restart time stop-clock system cpu and peripherals clocks stop but main clock oscillator continues to run at rated frequency reduced system power fast restart - no oscillator restart time slow system cpu cloc ks are slowed while peripheral clock and main clock oscillator run at rated frequency power dissipation sli ghtly higher than stop-clock continuous operation at low frequency fast all clocks and oscillators run at rated frequency highest power fastest response hs-82c85rh
12 fn3044.3 april 20, 2007 oscillator/clock start control once the oscillator is stopped (or committed to stop) or at power-on, the restart sequence is initiated by a high state on start or low state on res . if f/c is high, then restart occurs immediately after the start or res input is synchronized internally. this insures that stopped outputs (clk, pclk, osc and clk50) start cleanly with the proper phase relationship. if f/c is low (crystal oscillator mode), a high state on the start input or a low state on res causes the crystal oscillator to be restarted. the stopped outputs remain stopped, until the oscillator signal amplitude reaches the x1 schmitt trigger input threshol d voltage and 8192 cycles of the crystal oscillator output are counted by an internal counter. after this count is complete, the stopped outputs (clk, clk50, pclk) start cleanly with the proper phase relationships. typically, any input signal which meets the start input timing requirements can be used to start the hs-82c85rh. in many cases, this would be the int output from an hs-82c59a cmos priority interrupt controller (see figure 16). this output, wh ich is active high, can be connected to both the hs-82c85rh start pin and to the intr input on th e microprocessor. when the int output becomes ac tive (as a result of a ?restart? irq or a system reset), the oscillator/clock circuit on the hs-82c85rh will restart. upon completion of the appropriate restart sequence, the clk signal to the cpu will become active. the cpu can then respond to the still- pending interrupt request. oscillator/clock stop control the s0, s1, and s2 /stop control lines determine when the hs-82c85rh clock outputs or oscillator will stop. these three lines are designed to connect directly to the maximum mode hs-80c86rh status lines as shown in figure 17. when used in this configuration, the hs-82c85rh will automatically recognize a software halt command from the hs-80c86rh and stop the system clocks or oscillator. this allows complete software control of the stop function. if the hs-80c86rh is used in the minimum mode, the hs-82c85rh can be controlled using the s2 /stop input (with s0 and s1 held high). this can be done using the circuit shown in figure 18. since the hs-80c86rh, when executing a halt instruction in minimum mode, issues a single ale pulse with no corresponding bus signals (den remains high), the ale pulse will be clocked through the 74hc74 and put the hs-82c85rh into stop mode. hs-82c59a int hs-82c85rh clk hs-80c86rh start clk intr figure 16. start control using hs-82c59arh interrupt controller s2 s1 s0 min/max s2 / stop s1 s0 hs-80c86rh hs-82c85rh figure 17. stop control using hs-80c86rh maximum mode status lines hs-80c86rh microprocessor ale den reset min/max hs-82c85rh clock controller/ s0 s1 clk reset generator s2 /stop 1d 1q 2d 2q 3d 3q 4d 4q vdd clk 74hc74 quad d flip-flop with clear clr to hs-80c86rh and peripherals vdd figure 18. stop control using hs-80c86rh in minimum mode hs-82c85rh
13 fn3044.3 april 20, 2007 the hs-82c85rh status inputs s2 /stop , s1, s0 are sampled on the rising edge of clk. the oscillator (f/c low only) and clock outputs are stopped by s2 /stop , s1, s0 being in the lhh state on a low-to-high transition of clk. this lhh state must follow a passive hhh state occurring on the previous low-to-high clk trans ition. clk and clk50 will stop in the logic high state after two additional complete cycles of clk. pclk stops in its current state (high or low). this is true for both slow and fast mode operation. stop-oscillator mode when the hs-82c85rh is stopped while in the crystal mode (f/c low), the oscillator, in addi tion to all system clock signals (clk, clk50 and pclk), are stopped. clk and clk50 stop in the high state. pclk stops in its current state (high or low). with the oscillator stopped, hs-82c85rh power drops to its lowest level. all clocks and oscillators are stopped. all devices in the system which are driven by the hs-82c85rh go into the lowest power standby mode. the hs-82c85rh also goes into standby and requires a power supply current of less than 100ma. stop-clock mode when the hs-82c85rh is in the efi mode (f/c high) and a stop command is issued, al l system clock signals (clk, clk50 and pclk) are stopped. clk and clk50 stop in the high state. pclk stops in its current state (high or low). the hs-82c85rh can also provide its own efi source simply by connecting the osc output to the efi input and pulling the f/c input high. this puts the hs-82c85rh into the external frequency mode using its own oscillator as an external source signal (see figure 19). in this configuration, when the hs-82c85rh is stopped in the efi mode, the oscillator cont inues to run. only t he clocks to the cpu and peripherals (clk, clk50 and pclk) are stopped. clock slow/fast operation the slo /fst input determines whether the clk and clk50 outputs run at full speed (crystal or efi frequency divided by 3) or at slow speed (crystal or efi frequency divided by 768) (see figure 20). when in the slow mode, hs-82c85rh stop-clock and stop-oscillator functions oper ate in the same manner as in the fast mode, and the frequency of pclk is unaffected. the slow mode allows the cpu and the system to operate at a reduced rate wh ich, in turn, reduce s system power. for example, the operating power for the hs-80c86rh cpu is 10ma/mhz of clock frequency. when the slow mode is used in a typical 5mhz syst em, clk and clk50 run at approximately 20khz. at th is reduced frequency, the average operating current of the cpu drops to 200ma. adding the hs-80c86rh 500ma standby current brings the total current to 700ma. while the cpu and peripherals run slower and the hs-82c85rh clk and clk50 outputs switch at a reduced frequency, the main hs-82c85rh oscillator is still running at the maximum frequency (determined by the crystal or efi input frequency.) since cmos power is directly related to operating frequency, hs-82c85rh power supply current will typically be reduced by 25% - 35%. x1 efi f/ c s2 / stop s1 s0 x2 osc start v dd start control stop control figure 19. stop-clock mode in efi mode with oscillator as frequency source efi or osc pclk slo /fst clk clk50 figure 20. slow/fast timing overview hs-82c85rh
14 fn3044.3 april 20, 2007 internal logic requires that the slo /fst pin be held low for at least 195 oscillator or efi clock pulses before the slow mode command is recognized. th is requirement eliminates unwanted fast-to-slow mode frequency changes which could be caused by glitches or noise spikes. to guarantee fast mode recognition, the slo /fst pin must be held high for at least 3 osc or efi pulses. the hs-82c85rh will begin fast mode operation on the next pclk edge after fast command recognition. proper clk and clk50 phase relationships are maintained and minimum pulse width specifications are met. fast-to-slow or slow-to-fast mode changes will occur on the next rising or falling edge of pclk. it is important to remember that the transition time for operating frequency changes, which are dependent upon pclk, will vary with the hs-82c85rh oscillator or efi frequency. slow/fast mode control the hs-82c55arh programmabl e peripheral interface can be used to provide slow/fast mode control by connecting one of the port pins directly to the slo /fst pin (see figure 21). with the port pin configured as an output, software control of the slo /fst pin is provided by simply writing a logical one (fast mode) or logical zero (slow mode) to the corresponding port. port c is well-suited for this function due to its bit set and reset capabilities. alternate operating modes using alternate modes of operat ion (slow, stop-clock, stop- oscillator) will reduce the average system operating power dissipation in a static cmos system (see table 2). this does not mean that system speed or throughput must be reduced. when used appropriately, the slow, stop-clock, stop- oscillator modes can make your design more power-efficient while maintaining maxi mum system performance. oscillator the oscillator circuit of the hs-82c85rh is designed primarily for use with an external parallel resonant, fundamental mode crystal from which the basic operating frequency is derived. the crystal frequency must be three times the required cpu clock. x1 and x2 are the two crystal input connections. the output of the oscillator is buffered and available at the osc output (pin 18) for generation of other system timing signals. for the most stable operation of the oscillator (osc) output circuit, two capacitors (c1 = c2) are recommended. capacitors c1 and c2 are chosen such that their combined capacitance matches the load capacitance as specified by the crystal manufacturer. this insures operation within the frequency tolerance specified by the crystal manufacturer. the crystal/capacitor configuration and the formula used to determine the capacitor values are shown in figure 22. crystal specifications are shown in table 3. for additional information on crystal operation, see intersil publication tech brief 47. hs-82c85rh clock controller generator clk slo /fst clk d0 - 8 hs-80c86rh processor hs-82c55rh peripheral interface pc0 figure 21. slow/fast mode control using hs-82c55rh peripheral interface table 2. typical system power supply current for static cmos operating modes fast slow stop- clock stop- osc cpu frequency 5mhz 20khz dc dc xtal frequency 15mhz 15mhz 15mhz dc idd hs-80c86rh 50ma 2.5ma 250 a 250 a hs-82c85rh 24.7ma 16.9ma 14.1ma 24.4 a hs-82c08rh 1.0ma 10.0 a1.0 a1.0 a 82c82 1.7ma 6.5ma 1.0 a1.0 a hs-82c54rh 943 .0 a 915.0 a1.0 a1.0 a hs-82c55arh 3.2 a1.2 a1.0 a1.0 a 74hcxx + other 2.9ma 110.0 a 90.0 a 90.0 a hs-65262rh 4.0ma 50.0 a 10.0 a 10.0 a hs-6617rh 6.3ma 52.5 a 12.0 a 12.0 a note: all measurements taken at room temperature, vdd = +5.0v. power supply current levels will be dependent upon system configuration and frequency of operation. x1 x2 c 1 c 2 crystal 2.4mhz - 15mhz ct c1 c2 ? c1 c2 + ---------------------- (including stray capacitance) = figure 22. crystal connection hs-82c85rh
15 fn3044.3 april 20, 2007 frequency source selection the f/c input is a strapping pin that selects either the crystal oscillator or the efi input as the source frequency for clock generation. if the efi input is selected as the source, the oscillator section (osc out put) can be used independently for another clock source. if a cr ystal is not used, then crystal input x1 (pin 23) must be tied to vdd or gnd and x2 (pin 22) should be left open. if the efi mode is not used, then efi (pin 20) should be tied to vdd or gnd. clock generator the clock generator consists of two synchronous divide-by- three counters with special cl ear inputs that inhibit the counting. one counter generates a 33% duty cycle waveform (clk) and the other generates a 50% duty cycle waveform (clk50). these two counters are negative-edge synchronized, with the low- going transitions of both waveforms occurring on the same oscillator transition. the clk and clk50 output frequencie s are one-third of the base input frequency when slo /fst is high and are equal to the base input frequency divided by 768 when slo /fst is low. the clk output is a 33% duty cycle clock signal designed to drive the hs-80c86rh microprocessor directly. clk50 has a 50% duty cycle output synchronous with clk, designed to drive coprocessors and peripherals requiring a 50% duty cycle clock. pclk is a peripheral clock signal with an output frequency equal to the oscillator or efi frequency divided by 6. pclk has a 50% duty cycle. pclk is unaffected by slo /fst. when the hs-82c85rh is placed in the stop mode, pclk will remain in its current state (logic high or logic low) until a res or start command restarts the hs-82c85rh clock circuitry. pclk is negative-edge synchr onized with clk and clk50. since pclk continues to run at the same frequency regardless of the state of the slo /fst pin, it can be used by other devices in the system which need a fi xed high frequen cy clock. for example, pclk could be used to clock an hs-82c54rh programmable interval timer to produce a real-time clock for the system or as a baud rate generator to maintain serial data communications during slow mode operation. clock synchronization the clock synchronization (csync) input allows the output clocks to be synchronized with an external event (such as another hs-82c85rh clock signal). csync going active causes all clocks (clk, clk5 0 and pclk) to stop in the high state. it is necessary to synchronize the csync input to the efi clock using two flip-flops as shown in figure 23. multiple external flip-flops are necessa ry to minimize the occurrence of metastable (or indeterminate) states. ready synchronization two rdy inputs (rdy1, rdy2) are provided to accommodate two system buse s. each rdy input is qualified by its corresponding aen input (aen1 , aen2 ). reception of a valid rdy signal causes the hs-82c85rh to output ready high, informing the hs-80c86rh that the pending data transfer may be concluded (see hs-80c86rh data sheet system timing). synchronization is required for all asynchronous active- going edges of either rdy inpu t to guarantee that the rdy set up and hold times are met. inactive-going edges of rdy in normally ready systems do not require synch ronization but must satisfy rdy setup and hold as a matter of proper system design. the async input defines two modes of rdy synchronization operation. when async is low, two stages of synchronization are provided for active rdy input signals. positive-going asynchronous rdy inputs will first be synchronized to flip-flop one at the rising edge of clk (requiring a setup time tr1vch) and then synchronized to flip-flop two at the next falling edge of clk, after which time the ready output will go high. negative-going asynchronous rdy inputs will be synchronized directly to flip-flop two at the falling edge of clk, after which time the rdy output will go inactive. this mode of operation is intended for use by asynchronous (normally not ready) devices in the system which cannot be guaranteed by design to meet the required rdy setup timing (tr1vcl) on each bus cycle. when async is high or left open, the first rdy flip-flop is bypassed in the rdy synchronization logic. rdy inputs are synchronized by flip-flop two on the falling edge of clk before they are presented to the processor. this mode is available for synchronous devices that can be guaranteed to meet the required rdy setup time. async can be changed on every bus cycle to select the appropriate mode of synchronization for each device in the system. table 3. crystal specifications parameter typical crystal specification frequency 2.4mhz to 15mhz type of operation parallel resonant, fund. mode load capacitance 20pf or 32pf r series (max) 56 (f = 15mhz, c l = 32pf), 105 (f = 15mhz, c l = 20pf) efi csync d q > (to other hs-82c85rh dq > efi clk synch csync with hs-82c85rh(s) figure 23. csync synchronization methods hs-82c85rhs) hs-82c85rh
16 fn3044.3 april 20, 2007 die characteristics die dimensions: 2770 m x 3130 m x 483 m 25 m interface materials: glassivation: type: sio2 thickness: 8k ? 1k ? top metallization: type: al/si thickness: 11k ? 2k ? substrate: radiation hardened silicon gate, dielectric isolation backside finish: silicon assembly related information: substrate potential: unbiased (di) additional information: worst case current density: 1.6 x 10 4 a/cm 2 metallization mask layout hs-82c85rh (3) aen1 (2) pclk (1) csync (24) v dd (23) x1 (22) x2 (21) async rdy1 (4) ready (5) rdy2 (6) aen2 (7) clk (8) gnd (v ss )(9) clk50 (10) start (11) slo /fst (12) s0 (13) s1 (14) s2 /stop (15) m a s k (20) efi (19) f/c (18) osc (17) res (16) reset hs-82c85rh
17 fn3044.3 april 20, 2007 hs-82c85rh ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off- center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the finished lead surfac es, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k24.a mil-std-1835 cdfp4-f24 (f-6a, configuration b) 24 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.640 - 16.26 3 e 0.350 0.420 9.14 10.67 - e1 - 0.450 - 11.43 3 e2 0.180 - 4.57 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n24 24- rev. 0 5/18/94
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn3044.3 april 20, 2007 hs-82c85rh ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d24.6 mil-std-1835 cdip2-t24 (d-3, configuration c) 24 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 1.290 - 32.77 - e 0.500 0.610 12.70 15.49 - e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.120 0.200 3.05 5.08 - q 0.015 0.075 0.38 1.91 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n24 248 rev. 0 4/94

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